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» A spatial path scheduling algorithm for EDGE architectures
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FPL
2003
Springer
100views Hardware» more  FPL 2003»
15 years 2 months ago
Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core
In this paper we present a single-chip FPGA full encryptor/decryptor core design of the AES algorithm. Our design performs all of them, encryption, decryption and key scheduling pr...
Nazar A. Saqib, Francisco Rodríguez-Henr&ia...
IESS
2007
Springer
162views Hardware» more  IESS 2007»
15 years 3 months ago
Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs
Abstract This paper presents an embedded system design toolchain for automatic generation of parallel code runnable on symmetric multiprocessor systems from an initial sequential s...
Fabrizio Ferrandi, Luca Fossati, Marco Lattuada, G...
DAC
2008
ACM
15 years 10 months ago
Multithreaded simulation for synchronous dataflow graphs
Synchronous dataflow (SDF) has been successfully used in design tools for system-level simulation of wireless communication systems. Modern wireless communication standards involv...
Chia-Jui Hsu, José Luis Pino, Shuvra S. Bha...
MOBICOM
2012
ACM
13 years 1 days ago
Temporal reachability graphs
While a natural fit for modeling and understanding mobile networks, time-varying graphs remain poorly understood. Indeed, many of the usual concepts of static graphs have no obvi...
John Whitbeck, Marcelo Dias de Amorim, Vania Conan...
CORR
2011
Springer
142views Education» more  CORR 2011»
14 years 1 months ago
Taming Numbers and Durations in the Model Checking Integrated Planning System
The Model Checking Integrated Planning System (MIPS) has shown distinguished performance in the second and third international planning competitions. With its object-oriented fram...
Stefan Edelkamp