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» A spatial path scheduling algorithm for EDGE architectures
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DATE
2006
IEEE
91views Hardware» more  DATE 2006»
15 years 1 months ago
Efficient incremental clock latency scheduling for large circuits
The clock latency scheduling problem is usually solved on the sequential graph, also called register-to-register graph. In practice, the the extraction of the sequential graph for...
Christoph Albrecht
ACL
1996
14 years 11 months ago
Chart Generation
Charts constitute a natural uniform architecture for parsing and generation provided string position is replaced by a notion more appropriate to logical forms and that measures ar...
Martin Kay
FOCS
1997
IEEE
15 years 1 months ago
General Dynamic Routing with Per-Packet Delay Guarantees of O(distance + 1 / session rate)
A central issue in the design of modern communication networks is that of providing performance guarantees. This issue is particularly important if the networks support real-time t...
Matthew Andrews, Antonio Fernández, Mor Har...
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Voted
ESTIMEDIA
2004
Springer
15 years 3 months ago
Data assignment and access scheduling exploration for multi-layer memory architectures
Abstract— This paper presents an exploration framework which performs data assignment and access scheduling exploration for applications given a multilayer memory architecture. O...
Radoslaw Szymanek, Francky Catthoor, Krzysztof Kuc...
EDBT
2008
ACM
150views Database» more  EDBT 2008»
15 years 9 months ago
Finding time-dependent shortest paths over large graphs
The spatial and temporal databases have been studied widely and intensively over years. In this paper, we study how to answer queries of finding the best departure time that minim...
Bolin Ding, Jeffrey Xu Yu, Lu Qin