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» A spatial path scheduling algorithm for EDGE architectures
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ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
15 years 2 months ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan
112
Voted
IPPS
2010
IEEE
14 years 7 months ago
Tile QR factorization with parallel panel processing for multicore architectures
To exploit the potential of multicore architectures, recent dense linear algebra libraries have used tile algorithms, which consist in scheduling a Directed Acyclic Graph (DAG) of...
Bilel Hadri, Hatem Ltaief, Emmanuel Agullo, Jack D...
82
Voted
INFOCOM
2010
IEEE
14 years 8 months ago
On Channel-Discontinuity-Constraint Routing in Wireless Networks
Multi-channel wireless networks are increasingly being employed as infrastructure networks, e.g. in metro areas. Nodes in these networks frequently employ directional antennas to ...
Swaminathan Sankararaman, Alon Efrat, Srinivasan R...
INFOCOM
2007
IEEE
15 years 3 months ago
A Cross-Layer Architecture to Exploit Multi-Channel Diversity with a Single Transceiver
—The design of multi-channel multi-hop wireless mesh networks is centered around the way nodes synchronize when they need to communicate. However, existing designs are confined ...
Jay A. Patel, Haiyun Luo, Indranil Gupta
DATE
2004
IEEE
158views Hardware» more  DATE 2004»
15 years 1 months ago
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
We address the design of complex monolithic systems, where processing cores generate and consume a varying and large amount of data, thus bringing the communication links to the e...
Srinivasan Murali, Giovanni De Micheli