Sciweavers

194 search results - page 14 / 39
» A static power model for architects
Sort
View
SOCC
2008
IEEE
151views Education» more  SOCC 2008»
15 years 4 months ago
Failure analysis for ultra low power nano-CMOS SRAM under process variations
— Several design metrics have been used in the past to evaluate the SRAM cell stability. However, most of them fail to provide the exact stability figures as shown in this paper...
Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Sar...
ISVLSI
2005
IEEE
129views VLSI» more  ISVLSI 2005»
15 years 3 months ago
Reduction of Direct Tunneling Power Dissipation during Behavioral Synthesis of Nanometer CMOS Circuits
— Direct tunneling current is the major component of static power dissipation of a CMOS circuit for technology below 65nm, where the gate dielectric (SiO2) is very low. We intuit...
Saraju P. Mohanty, Ramakrishna Velagapudi, Valmiki...
75
Voted
ASPDAC
2007
ACM
119views Hardware» more  ASPDAC 2007»
15 years 1 months ago
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng,...
IISWC
2006
IEEE
15 years 3 months ago
Performance Cloning: A Technique for Disseminating Proprietary Applications as Benchmarks
Many embedded real world applications are intellectual property, and vendors hesitate to share these proprietary applications with computer architects and designers. This poses a ...
Ajay Joshi, Lieven Eeckhout, Robert H. Bell Jr., L...
ICCAD
1998
IEEE
120views Hardware» more  ICCAD 1998»
15 years 1 months ago
Communication synthesis for distributed embedded systems
Designers of distributed embedded systems face many challenges in determining the appropriate tradeoffs to make when defining a system architecture or retargeting an existing desi...
Ross B. Ortega, Gaetano Borriello