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» A static power model for architects
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ISPASS
2010
IEEE
15 years 4 months ago
Synthesizing memory-level parallelism aware miniature clones for SPEC CPU2006 and ImplantBench workloads
Abstract—We generate and provide miniature synthetic benchmark clones for modern workloads to solve two pre-silicon design challenges, namely: 1) huge simulation time (weeks to m...
Karthik Ganesan, Jungho Jo, Lizy K. John
CASES
2007
ACM
15 years 1 months ago
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters....
Rahul Nagpal, Arvind Madan, Bharadwaj Amrutur, Y. ...
ISPASS
2005
IEEE
15 years 3 months ago
Studying Thermal Management for Graphics-Processor Architectures
We have previously presented Qsilver, a flexible simulation system for graphics architectures. In this paper we describe our extensions to this system, which we use— instrument...
Jeremy W. Sheaffer, Kevin Skadron, David P. Luebke
HICSS
2012
IEEE
346views Biometrics» more  HICSS 2012»
13 years 5 months ago
The Fundamental Concept of Unified Generalized Model and Data Representation for New Applications in the Future Grid
The concept of interoperability of data and model as presented in this paper is viewed as being very useful for implementing variety of future applications related to power system...
Mladen Kezunovic, Santiago Grijalva, Papiya Dutta,...
63
Voted
ACSD
2010
IEEE
219views Hardware» more  ACSD 2010»
14 years 7 months ago
The Model Checking View to Clock Gating and Operand Isolation
Abstract--Clock gating and operand isolation are two techniques to reduce the power consumption in state-of-the-art hardware designs. Both approaches basically follow a two-step pr...
Jens Brandt, Klaus Schneider, Sumit Ahuja, Sandeep...