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» A static power model for architects
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FPL
2008
Springer
141views Hardware» more  FPL 2008»
14 years 11 months ago
An analytical model describing the relationships between logic architecture and FPGA density
This paper describes an analytical model, based principally on Rent's Rule, that relates logic architectural parameters to the area efficiency of an FPGA. In particular, the ...
Andrew Lam, Steven J. E. Wilton, Philip Heng Wai L...
DATE
2000
IEEE
113views Hardware» more  DATE 2000»
15 years 2 months ago
Static Timing Analysis of Embedded Software on Advanced Processor Architectures
This paper examines several techniques for static timing analysis. In detail, the first part of the paper analyzes the connection of prediction accuracy (worst case execution tim...
André Hergenhan, Wolfgang Rosenstiel
ISQED
2010
IEEE
170views Hardware» more  ISQED 2010»
14 years 11 months ago
New SRAM design using body bias technique for ultra low power applications
A new SRAM design is proposed. Body biasing improves the static noise margin (SNM) improved by at least 15% compared to the standard cells. Through using this technique, lowering ...
Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Yn...
ECOOP
1998
Springer
15 years 1 months ago
Reflection for Statically Typed Languages
Abstract. An object-oriented language that permits changing the behavior of a class or of a single object is said to support computational reflection. Existing reflective facilitie...
José de Oliveira Guimarães
RSP
2003
IEEE
132views Control Systems» more  RSP 2003»
15 years 2 months ago
Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
Prabhat Mishra, Arun Kejariwal, Nikil Dutt