194 search results - page 7 / 39 » A static power model for architects |
FPL
2009
Springer
15 years 2 months ago
2009
Springer
This paper presents a methodology for estimating and optimising FPGA routing fabrics using high-level modelling and convex optimisation techniques. Experimental methods for explor...
VLSID
2002
IEEE
15 years 10 months ago
2002
IEEE
Verification is one of the most complex and expensive tasks in the current Systems-on-Chip (SOC) design process. Many existing approaches employ a bottom-up approach to pipeline v...
CORR
2006
Springer
14 years 9 months ago
2006
Springer
The well-known problem of state space explosion in model checking is even more critical when applying this technique to programming languages, mainly due to the presence of complex...
ICSE
2008
IEEE-ACM
15 years 10 months ago
2008
IEEE-ACM
Static analysis tools report software defects that may or may not be detected by other verification methods. Two challenges complicating the adoption of these tools are spurious f...
CODES
2008
IEEE
15 years 4 months ago
2008
IEEE
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...