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» A study of slipstream processors
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HPCA
2005
IEEE
15 years 11 months ago
A Performance Comparison of DRAM Memory System Optimizations for SMT Processors
Memory system optimizations have been well studied on single-threaded systems; however, the wide use of simultaneous multithreading (SMT) techniques raises questions over their ef...
Zhichun Zhu, Zhao Zhang
ISCA
1999
IEEE
110views Hardware» more  ISCA 1999»
15 years 3 months ago
Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor
Providing adequate data bandwidth is extremely important for a wide-issue superscalar processor to achieve its full performance potential. Adding a large number of ports to a data...
Sangyeun Cho, Pen-Chung Yew, Gyungho Lee
AE
2009
Springer
15 years 6 days ago
On-Line, On-Board Evolution of Robot Controllers
This paper reports on a feasibility study into the evolution of robot controllers during the actual operation of robots (on-line), using only the computational resources within the...
Nicolas Bredeche, Evert Haasdijk, A. E. Eiben
85
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HPCA
2005
IEEE
15 years 11 months ago
Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a Chip Multi-Processor (CMP) architecture. Cache sharing impacts threads non-u...
Dhruba Chandra, Fei Guo, Seongbeom Kim, Yan Solihi...
ISCA
2008
IEEE
116views Hardware» more  ISCA 2008»
15 years 5 months ago
3D-Stacked Memory Architectures for Multi-core Processors
Three-dimensional integration enables stacking memory directly on top of a microprocessor, thereby significantly reducing wire delay between the two. Previous studies have examin...
Gabriel H. Loh