1055 search results - page 15 / 211 » A system level perspective on branch architecture performanc... |
ISSS
2002
IEEE
15 years 6 months ago
2002
IEEE
We present the modeling of the high-level design of a next generation network switch from the perspective of a ComputerAided Design (CAD) team within the larger context of a desig...
VLSID
2005
IEEE
16 years 2 months ago
2005
IEEE
Inter-wire coupling is a major source of power consumption and delay faults for on-chip buses implemented in UDSM SoC Systems. Elimination or minimization of such faults is crucia...
127
Voted
JPDC
2000
15 years 1 months ago
2000
: SIMD arrays are likely to become increasingly important as coprocessors in domain specific systems as architects continue to leverage RAM technology in their design. The problem ...
108
click to vote
DAC
2001
ACM
16 years 2 months ago
2001
ACM
In this paper, we study the problem of performance-driven multi-level circuit clustering with application to hierarchical FPGA designs. We first show that the performance-driven m...
116
Voted
ISVLSI
2008
IEEE
15 years 8 months ago
2008
IEEE
Future embedded systems will integrate hundreds of processors. Current design space exploration methods cannot cope with such a complexity. It is mandatory to extend these methods...