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SCAM
2005
IEEE
15 years 7 months ago
Control Flow Graph Reconstruction for Assembly Language Programs with Delayed Instructions
Most software for embedded systems, including digital signal processing systems, is coded in assembly language. For both understanding the software and for reverse compiling it to...
Nerina Bermudo, Andreas Krall, R. Nigel Horspool
IPPS
2006
IEEE
15 years 8 months ago
A high level SoC power estimation based on IP modeling
Current electronic system design requires to be concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is esti...
David Elléouet, Nathalie Julien, Dominique ...
ET
2007
101views more  ET 2007»
15 years 1 months ago
Towards Nanoelectronics Processor Architectures
In this paper, we focus on reliability, one of the most fundamental and important challenges, in the nanoelectronics environment. For a processor architecture based on the unreliab...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
DAC
1999
ACM
15 years 6 months ago
Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification
We present our practical experience in the modeling and integration of cycle/phase-accurate instruction set architecture (ISA) models of digital signal processors (DSPs) with othe...
Lisa M. Guerra, Joachim Fitzner, Dipankar Talukdar...
NETWORK
2007
145views more  NETWORK 2007»
15 years 1 months ago
Analysis of Shared Memory Priority Queues with Two Discard Levels
— Two rate SLAs become increasingly popular in today’s Internet, allowing a customer to save money by paying one price for committed traffic and a much lower price for additio...
Shlomi Bergida, Yuval Shavitt