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CONEXT
2006
ACM
15 years 8 months ago
Proposition of a cross-layer architecture model for the support of QoS in ad-hoc networks
Due to the lack of built-in quality of service support, IEEE 802.11 ad-hoc networks presents serious defies in meeting the demands of multimedia applications. To overcome such ch...
Wafa Berrayana, Habib Youssef, Stéphane Loh...
ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
15 years 6 months ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for application−specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
108
Voted
CASES
2005
ACM
15 years 3 months ago
Compilation techniques for energy reduction in horizontally partitioned cache architectures
Horizontally partitioned data caches are a popular architectural feature in which the processor maintains two or more data caches at the same level of hierarchy. Horizontally part...
Aviral Shrivastava, Ilya Issenin, Nikil Dutt
ENGL
2006
99views more  ENGL 2006»
15 years 1 months ago
A Patient Specific Neural Networks (MLP) for Optimization of Fuzzy Outputs in Classification of Epilepsy Risk Levels from EEG Si
In recent years Neural Networks have been widely used as pattern and statistical classifiers in bio medical engineering. Most research to date using hybrid systems (Fuzzy-Neuro) fo...
R. Sukanesh, R. Harikumar
133
Voted
DSN
2007
IEEE
15 years 8 months ago
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...
Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Josep...