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LCTRTS
1998
Springer
15 years 6 months ago
Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques
Abstract. Previously published methods for estimation of the worstcase execution time on contemporary processors with complex pipelines and multi-level memory hierarchies result in...
Thomas Lundqvist, Per Stenström
DATE
2006
IEEE
140views Hardware» more  DATE 2006»
15 years 8 months ago
A hybrid framework for design and analysis of fault-tolerant architectures
It is anticipated that self assembled ultra-dense nanomemories will be more susceptible to manufacturing defects and transient faults than conventional CMOS-based memories, thus t...
Debayan Bhaduri, Sandeep K. Shukla, Deji Coker, Va...
ISVC
2007
Springer
15 years 8 months ago
A Vision-Based Architecture for Intent Recognition
Abstract. Understanding intent is an important aspect of communication among people and is an essential component of the human cognitive system. This capability is particularly rel...
Alireza Tavakkoli, Richard Kelley, Christopher Kin...
122
Voted
CODES
2008
IEEE
15 years 3 months ago
Profiling of lossless-compression algorithms for a novel biomedical-implant architecture
In view of a booming market for microelectronic implants, our ongoing research work is focusing on the specification and design of a novel biomedical microprocessor core targeting...
Christos Strydis, Georgi Gaydadjiev
CC
2008
Springer
123views System Software» more  CC 2008»
15 years 4 months ago
Automatic Transformation of Bit-Level C Code to Support Multiple Equivalent Data Layouts
Portable low-level C programs must often support multiple equivalent in-memory layouts of data, due to the byte or bit order of the compiler, architecture, or external data formats...
Marius Nita, Dan Grossman