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IISWC
2008
IEEE
15 years 8 months ago
Accelerating multi-core processor design space evaluation using automatic multi-threaded workload synthesis
The design and evaluation of microprocessor architectures is a difficult and time-consuming task. Although small, handcoded microbenchmarks can be used to accelerate performance e...
Clay Hughes, Tao Li
MVA
1992
188views Computer Vision» more  MVA 1992»
15 years 3 months ago
The Programmable and Configurable Low Level Vision Unit of the HERMIA Machine
In this work the Low Level Vision Unit (LLVU) of the Heterogeneous and Reconfigurable Machine for Image Analysis (HERMIA) is described. The LLVU consists of the innovative integra...
Gaetano Gerardi, Giancarlo Parodi
CLUSTER
2006
IEEE
15 years 8 months ago
Open MPI: A High-Performance, Heterogeneous MPI
The growth in the number of generally available, distributed, heterogeneous computing systems places increasing importance on the development of user-friendly tools that enable ap...
Richard L. Graham, Galen M. Shipman, Brian Barrett...
RSP
2006
IEEE
102views Control Systems» more  RSP 2006»
15 years 8 months ago
Rapid Resource-Constrained Hardware Performance Estimation
In a hardware-software co-design environment, an application is partitioned into modules. Each module is then mapped either to software or to hardware. The mapping process is driv...
Basant Kumar Dwivedi, Arun Kejariwal, M. Balakrish...
136
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TECS
2008
122views more  TECS 2008»
15 years 1 months ago
Quantitative analysis of the speed/accuracy trade-off in transaction level modeling
tion. Transaction Level Modeling (TLM) has been proposed to abstract communication for highspeed system simulation and rapid design space exploration. Although being widely accepte...
Gunar Schirner, Rainer Dömer