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APCSAC
2005
IEEE
15 years 5 months ago
The Challenges of Massive On-Chip Concurrency
Moore’s law describes the growth in on-chip transistor density, which doubles every 18 to 24 months and looks set to continue for at least a decade and possibly longer. This grow...
Kostas Bousias, Chris R. Jesshope
SAMOS
2009
Springer
15 years 6 months ago
Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration
System-level computer architecture simulations create large volumes of simulation data to explore alternative architectural solutions. Interpreting and drawing conclusions from thi...
Toktam Taghavi, Mark Thompson, Andy D. Pimentel
CA
2002
IEEE
15 years 4 months ago
A Hybrid Dynamical Systems Approach to Intelligent Low-Level Navigation
Animated characters may exhibit several kinds of dynamic intelligence when performing low-level navigation (i.e., navigation on a local perceptual scale): They decide among differ...
Eric Aaron, Harold C. Sun, Franjo Ivancic, Dimitri...
DATE
2003
IEEE
117views Hardware» more  DATE 2003»
15 years 5 months ago
Exploring SW Performance Using SoC Transaction-Level Modeling
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
Imed Moussa, Thierry Grellier, Giang Nguyen
IWOMP
2009
Springer
15 years 4 months ago
Dynamic Task and Data Placement over NUMA Architectures: An OpenMP Runtime Perspective
Abstract. Exploiting the full computational power of current hierarchical multiprocessor machines requires a very careful distribution of threads and data among the underlying non-...
François Broquedis, Nathalie Furmento, Bric...