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» A tale of two synchronizing clocks
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TVLSI
2010
14 years 4 months ago
A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors
A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost, flexible routing capability, and supports globally asynchronous loc...
Zhiyi Yu, Bevan M. Baas

Publication
279views
16 years 7 months ago
Potential Networking Applications of Global Positioning Systems (GPS)
Global Positioning System (GPS) Technology allows precise determination of location, velocity, direction, and time. The price of GPS receivers is falling rapidly and the applicatio...
G. Dommety and Raj Jain
ENTCS
2006
168views more  ENTCS 2006»
14 years 9 months ago
A Functional Programming Framework for Latency Insensitive Protocol Validation
Latency insensitive protocols (LIPs) have been proposed as a viable means to connect synchronous IP blocks via long interconnects in a system-on-chip. The reason why one needs to ...
Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla...
EMSOFT
2007
Springer
15 years 3 months ago
Loosely time-triggered architectures based on communication-by-sampling
We address the problem of mapping a set of processes which communicate synchronously on a distributed platform. The Time Triggered Architecture (TTA) proposed by Kopetz for the co...
Albert Benveniste, Paul Caspi, Marco Di Natale, Cl...
PAAPP
2010
131views more  PAAPP 2010»
14 years 7 months ago
Accurately measuring overhead, communication time and progression of blocking and nonblocking collective operations at massive s
Accurate, reproducible and comparable measurement of the overheads, communication times and progression behavior of blocking and nonblocking collective operations is a complicated...
Torsten Hoefler, Timo Schneider, Andrew Lumsdaine