118 search results - page 18 / 24 » A technique for minimizing power during FPGA placement |
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INFOCOM
2012
IEEE
13 years 1 days ago
2012
IEEE
—This paper considers a component-level deceleration technique in BS operation, called speed-scaling, that is more conservative than entirely shutting down BSs, yet can conserve ...
WSC
2000
14 years 11 months ago
2000
Computation of power control calculations is one of the most time-consuming aspects of simulating wireless communication systems. These calculations are critical to understanding ...
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DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
Power gating is one of the most effective techniques in reducing the standby leakage current of VLSI circuits. In this paper we introduce a new approach for sleep transistor sizin...
DAC
2005
ACM
15 years 10 months ago
2005
ACM
In this paper we present a system level technique for mapping large, multiple-IP-block designs to channel-width constrained FPGAs. Most FPGA clustering tools [2, 3, 11] aim to red...
FCCM
2000
IEEE
15 years 2 months ago
2000
IEEE
Data compression techniques based on Lempel-Ziv (LZ) algorithm are widely used in a variety of applications, especially in data storage and communications. However, since the LZ a...