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» A timing-constrained simultaneous global routing algorithm
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ISPD
2005
ACM
205views Hardware» more  ISPD 2005»
15 years 3 months ago
Coupling aware timing optimization and antenna avoidance in layer assignment
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
Di Wu, Jiang Hu, Rabi N. Mahapatra
ISPD
2012
ACM
289views Hardware» more  ISPD 2012»
13 years 5 months ago
Keep it straight: teaching placement how to better handle designs with datapaths
As technology scales and frequency increases, a new design style is emerging, referred to as hybrid designs, which contain a mixture of random logic and datapath standard cell com...
Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanat...
ASPDAC
1998
ACM
101views Hardware» more  ASPDAC 1998»
15 years 1 months ago
An Integrated Flow for Technology Remapping and Placement of Sub-half-micron Circuits
ABSTRACT - This paper presents a new design flow, FPDSiMPA, and a set of techniques for synthesizing high-performance sub-half micron logic circuits. FPD-SiMPA consists of logic p...
Jinan Lou, Amir H. Salek, Massoud Pedram
VLDB
2007
ACM
135views Database» more  VLDB 2007»
15 years 3 months ago
Self-Organizing Schema Mappings in the GridVine Peer Data Management System
GridVine is a Peer Data Management System based on a decentralized access structure. Built following the principle of data independence, it separates a logical layer – where dat...
Philippe Cudré-Mauroux, Suchit Agarwal, Adr...