48 search results - page 3 / 10 » AHIR: A Hardware Intermediate Representation for Hardware Ge... |
IPPS
2006
IEEE
14 years 8 days ago
2006
IEEE
Modern FPGA platforms provide the hardware and software infrastructure for building a bus-based System on Chip (SoC) that meet the applications requirements. The designer can cust...
ISCA
2007
IEEE
14 years 17 days ago
2007
IEEE
Speculative compiler optimizations are effective in improving both single-thread performance and reducing power consumption, but their implementation introduces significant compl...
DATE
2009
IEEE
14 years 1 months ago
2009
IEEE
Abstract - This paper describes an efficient graphbased method to optimize data-flow expressions for best hardware implementation. The method is based on factorization, common su...
DAC
1995
ACM
13 years 9 months ago
1995
ACM
— Software components for embedded reactive real-time applications must satisfy tight code size and runtime constraints. Cooperating finite state machines provide a convenient i...
FPL
2009
Springer
13 years 10 months ago
2009
Springer
High-Level Synthesis (HLS) is the field of transforming a high-level programming language, such as C, into a register transfer level(RTL) description of the design. In HLS, Binary...