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ISSS
2002
IEEE
127views Hardware» more  ISSS 2002»
15 years 6 months ago
Validation in a Component-Based Design Flow for Multicore SoCs
Currently, since many SoCs include heterogeneous components such as CPUs, DSPs, ASICs, memories, buses, etc., system integration becomes a major step in the design flow. To enable...
Ahmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima,...
107
Voted
ITICSE
2006
ACM
15 years 7 months ago
WADEIn II: a case for adaptive explanatory visualization
Adaptive explanatory visualization is an attempt to integrate two promising approaches to program visualization: adaptive visualization and explanatory visualization. The goal of ...
Peter Brusilovsky, Tomasz D. Loboda
114
Voted
VLSID
2000
IEEE
79views VLSI» more  VLSID 2000»
15 years 6 months ago
Inductive Noise Reduction at the Architectural Level
A methodology for reducing ground bounce in typical microprocessors and image processing architectures has been described. As we approach Gigascale Integration, chip power consump...
Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Viv...
ISLPED
1999
ACM
84views Hardware» more  ISLPED 1999»
15 years 6 months ago
An architectural solution for the inductive noise problem due to clock-gating
As we approach Gigascale Integration, chip power consumption is becoming a critical system parameter. Clock-gating idle units provides needed reductions in power consumption. Howe...
Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Viv...
DEDS
2002
97views more  DEDS 2002»
15 years 1 months ago
N-dimensional Cell-DEVS Models
This article presents an extension to the timed binary Cell-DEVS paradigm. The goal is to allow the modelling of n-dimensional generic cell spaces, including transport or inertial...
Gabriel A. Wainer, Norbert Giambiasi