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FMCAD
2009
Springer
15 years 5 months ago
Finding heap-bounds for hardware synthesis
Abstract—Dynamically allocated and manipulated data structures cannot be translated into hardware unless there is an upper bound on the amount of memory the program uses during a...
Byron Cook, Ashutosh Gupta, Stephen Magill, Andrey...
ISCAS
2008
IEEE
102views Hardware» more  ISCAS 2008»
15 years 5 months ago
Asynchronous balanced gates tolerant to interconnect variability
Abstract— Existing methods of gate level power attack countermeasures depend on exact capacitance matching of the dual-rail data outputs of each gate. Process variability and a l...
Konrad J. Kulikowski, Vyas Venkataraman, Zhen Wang...
SIPS
2006
IEEE
15 years 5 months ago
Partly Parallel Overlapped Sum-Product Decoder Architectures for Quasi-Cyclic LDPC Codes
Abstract— In this paper, we propose partly parallel architectures based on optimal overlapped sum-product (OSP) decoding. To ensure high throughput and hardware utilization effi...
Ning Chen, Yongmei Dai, Zhiyuan Yan
ICMCS
2005
IEEE
123views Multimedia» more  ICMCS 2005»
15 years 4 months ago
An iterative power allocation algorithm in OFDM system based on power relaxation
Abstract— We present an efficient algorithm for power allocation and bit loading in multi-user OFDM system. We starts with the close-form optimum power solution based on ideal c...
Ju Wang, Jonathan C. L. Liu
RSP
2005
IEEE
207views Control Systems» more  RSP 2005»
15 years 4 months ago
Design Exploration and HW/SW Rapid Prototyping for Real-Time System Design
Embedded signal processing systems are usually associated with real-time constraints and/or high data rates so that fully software implementation are often not satisfactory. In th...
Sylvain Huet, Emmanuel Casseau, Olivier Pasquier