197 search results - page 10 / 40 » Abstraction Techniques for Validation Coverage Analysis and ... |
100
Voted
KBSE
2007
IEEE
15 years 6 months ago
2007
IEEE
We present CESE, a tool that combines exhaustive enumeration of test inputs from a structured domain with symbolic execution driven test generation. We target programs whose valid...
121
Voted
DATE
2009
IEEE
15 years 7 months ago
2009
IEEE
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
KBSE
1998
IEEE
15 years 4 months ago
1998
IEEE
Structural testing criteria are mandated in many software development standards and guidelines. The process of generating test-data to achieve 100 coverage of a given structural c...
104
Voted
DATE
1997
IEEE
15 years 4 months ago
1997
IEEE
A new method for state justi cation is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is use...
140
Voted
ICST
2010
IEEE
14 years 11 months ago
2010
IEEE
Abstract—Software Product Lines (SPL) are difficult to validate due to combinatorics induced by variability across their features. This leads to combinatorial explosion of the n...