279 search results - page 6 / 56 » Abstraction and refinement techniques in automated design de... |
GLVLSI
2009
IEEE
15 years 1 months ago
2009
IEEE
Design debug remains one of the major bottlenecks in the VLSI design cycle today. Existing automated solutions strive to aid engineers in reducing the debug effort by identifying ...
SAMOS
2007
Springer
15 years 3 months ago
2007
Springer
Abstract. Contemporary SoC designs ask for system-level debugging tools suitable to heterogeneous platforms. Such tools will have to rely on some low-level model-driven debugging e...
FDL
2007
IEEE
15 years 3 months ago
2007
IEEE
Since its first release the system level language SystemC had a significant impact on various areas in VLSI-CAD. One remarkable benefit of SystemC lies in the of abstraction le...
FMCAD
2009
Springer
15 years 4 months ago
2009
Springer
—Given an erroneous design, functional verification returns an error trace exhibiting a mismatch between the specification and the implementation of a design. Automated design ...
DAC
2009
ACM
15 years 10 months ago
2009
ACM
Recent improvements in design verification strive to automate error detection and greatly enhance engineers' ability to detect functional errors. However, the process of diag...