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» Abstraction-guided synthesis of synchronization
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DAC
2000
ACM
16 years 1 days ago
Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization
In this paper, we propose a technique to implement communication protocols as hardware circuits using a model of concurrent EFSMs with multi-way synchronization. Since use of mult...
Hisaaki Katagiri, Keiichi Yasumoto, Akira Kitajima...
ASPDAC
2004
ACM
75views Hardware» more  ASPDAC 2004»
15 years 4 months ago
A thread partitioning algorithm in low power high-level synthesis
This paper proposes a thread partitioning algorithm in low power high-level synthesis. The algorithm is applied to high-level synthesis systems. In the systems, we can describe pa...
Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Ta...
ICCAD
1994
IEEE
104views Hardware» more  ICCAD 1994»
15 years 3 months ago
Module selection and data format conversion for cost-optimal DSP synthesis
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear p...
Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi
HASE
1997
IEEE
15 years 3 months ago
Automated Computation of Decomposable Synchronization Conditions
: The most important aspect of concurrent and distributed computation is the interaction between system components. Integration of components into a system requires some synchroniz...
Gilberto Matos, James M. Purtilo, Elizabeth L. Whi...
ACSD
2001
IEEE
134views Hardware» more  ACSD 2001»
15 years 2 months ago
Embedding Imperative Synchronous Languages in Interactive Theorem Provers
We present a new way to define the semantics of imperative synchronous languages by means of separating the control and the data flow. The control flow is defined by predicates th...
Klaus Schneider