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133
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MICRO
2010
IEEE
170views Hardware» more  MICRO 2010»
15 years 1 months ago
Tolerating Concurrency Bugs Using Transactions as Lifeguards
Abstract--Parallel programming is hard, because it is impractical to test all possible thread interleavings. One promising approach to improve a multi-threaded program's relia...
Jie Yu, Satish Narayanasamy
139
Voted
MICRO
2010
IEEE
172views Hardware» more  MICRO 2010»
15 years 1 months ago
Architectural Support for Fair Reader-Writer Locking
Abstract--Many shared-memory parallel systems use lockbased synchronization mechanisms to provide mutual exclusion or reader-writer access to memory locations. Software locks are i...
Enrique Vallejo, Ramón Beivide, Adriá...
123
Voted
MICRO
2010
IEEE
270views Hardware» more  MICRO 2010»
15 years 1 months ago
Many-Thread Aware Prefetching Mechanisms for GPGPU Applications
Abstract-- We consider the problem of how to improve memory latency tolerance in massively multithreaded GPGPUs when the thread-level parallelism of an application is not sufficien...
Jaekyu Lee, Nagesh B. Lakshminarayana, Hyesoon Kim...
NAS
2010
IEEE
15 years 1 months ago
A Probabilistic Routing Protocol for Heterogeneous Sensor Networks
The past five years witnessed a rapid development in wireless sensor networks, which have been widely used in military and civilian applications. Due to different requirements in t...
Yuefei Hu, Wenzhong Li, Xiao Chen, Xin Chen, Sangl...
137
Voted
NOCS
2010
IEEE
15 years 1 months ago
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing
Abstract--The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face...
Samuel Rodrigo, Jose Flich, Antoni Roca, Simone Me...
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