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GRAPHICSINTERFACE
2003
14 years 11 months ago
Hardware-Accelerated Visual Hull Reconstruction and Rendering
We present a novel algorithm for simultaneous visual hull reconstruction and rendering by exploiting off-theshelf graphics hardware. The reconstruction is accomplished by projecti...
Ming Li, Marcus A. Magnor, Hans-Peter Seidel
ICASSP
2011
IEEE
14 years 1 months ago
Real-time DVB-S2 LDPC decoding on many-core GPU accelerators
It is well known that LDPC decoding is computationally demanding and one of the hardest signal operations to parallelize. Beyond data dependencies that restrict the decoding of a ...
Gabriel Falcão Paiva Fernandes, Joao Andrad...
FPGA
2012
ACM
285views FPGA» more  FPGA 2012»
13 years 5 months ago
Optimizing SDRAM bandwidth for custom FPGA loop accelerators
Memory bandwidth is critical to achieving high performance in many FPGA applications. The bandwidth of SDRAM memories is, however, highly dependent upon the order in which address...
Samuel Bayliss, George A. Constantinides
BMCBI
2008
214views more  BMCBI 2008»
14 years 9 months ago
Accelerating String Set Matching in FPGA Hardware for Bioinformatics Research
Background: This paper describes techniques for accelerating the performance of the string set matching problem with particular emphasis on applications in computational proteomic...
Yoginder S. Dandass, Shane C. Burgess, Mark Lawren...
BMCBI
2007
144views more  BMCBI 2007»
14 years 9 months ago
Accelerated search for biomolecular network models to interpret high-throughput experimental data
Background: The functions of human cells are carried out by biomolecular networks, which include proteins, genes, and regulatory sites within DNA that encode and control protein e...
Suman Datta, Bahrad A. Sokhansanj