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ISCA
2005
IEEE
134views Hardware» more  ISCA 2005»
15 years 3 months ago
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
Nathan Clark, Jason A. Blome, Michael L. Chu, Scot...
FPGA
2008
ACM
133views FPGA» more  FPGA 2008»
14 years 11 months ago
Vector processing as a soft-core CPU accelerator
The currently accepted method of accelerating applications in FPGA soft processor systems is to design a custom hardware accelerator. This paper suggests the alternative approach ...
Jason Yu, Guy Lemieux, Christopher Eagleston
99
Voted
BMCBI
2008
211views more  BMCBI 2008»
14 years 10 months ago
CUDA compatible GPU cards as efficient hardware accelerators for Smith-Waterman sequence alignment
Background: Searching for similarities in protein and DNA databases has become a routine procedure in Molecular Biology. The Smith-Waterman algorithm has been available for more t...
Svetlin Manavski, Giorgio Valle
ICML
2009
IEEE
15 years 11 months ago
Large-scale deep unsupervised learning using graphics processors
The promise of unsupervised learning methods lies in their potential to use vast amounts of unlabeled data to learn complex, highly nonlinear models with millions of free paramete...
Rajat Raina, Anand Madhavan, Andrew Y. Ng
IV
2010
IEEE
134views Visualization» more  IV 2010»
14 years 8 months ago
Molecular Rendering with Medieval and Renaissance Color Theory
—This paper describes the application of Medieval and Renaissance color theory to the computer graphic rendering of molecular models. In particular, Alberti’s and Cennini’s c...
Francis T. Marchese, Suzanne M. Marchese