Sciweavers

439 search results - page 16 / 88
» Accelerating multi-core simulators
Sort
View
JCM
2007
76views more  JCM 2007»
14 years 9 months ago
Scheduling Small Packets in IPSec Multi-accelerator Based Systems
—IPSec is a suite of protocols that adds security to communications at the IP level. Protocols within the IPSec suite make extensive use of cryptographic algorithms. Since these ...
Antonio Vincenzo Taddeo, Alberto Ferrante, Vincenz...
IPPS
2008
IEEE
15 years 4 months ago
Energy efficient packet classification hardware accelerator
Packet classification is an important function in a router’s line-card. Although many excellent solutions have been proposed in the past, implementing high speed packet classifi...
Alan Kennedy, Xiaojun Wang, Bin Liu
ICPP
2009
IEEE
15 years 4 months ago
Exploiting Simulation Slack to Improve Parallel Simulation Speed
Parallel simulation is a technique to accelerate microarchitecture simulation of CMPs by exploiting the inherent parallelism of CMPs. In this paper, we explore the simulation para...
Jianwei Chen, Murali Annavaram, Michel Dubois
TR
2010
128views Hardware» more  TR 2010»
14 years 4 months ago
Strategy for Planning Accelerated Life Tests With Small Sample Sizes
Previous work on planning accelerated life tests has been based on large-sample approximations to evaluate test plan properties. In this paper, we use more accurate simulation met...
Haiming Ma, William Q. Meeker
FPL
2006
Springer
211views Hardware» more  FPL 2006»
15 years 1 months ago
Comparing FPGAs to Graphics Accelerators and the Playstation 2 Using a Unified Source Description
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony's PlayStation 2 vector units offer scope for hardware acceleration of applications. We compa...
Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckm...