1057 search results - page 42 / 212 » Accelerating the LSTRS Algorithm |
128
Voted
INTENSIVE
2009
IEEE
15 years 7 months ago
2009
IEEE
In this paper an optimized k-means implementation on the graphics processing unit (GPU) is presented. NVIDIA’s Compute Unified Device Architecture (CUDA), available from the G8...
121
Voted
EURODAC
1990
IEEE
15 years 4 months ago
1990
IEEE
In this paper an efficient cone oriented circuit partitioning method is presented, which significantly speeds up automatic test pattern generation for combinational circuits. The ...
ARC
2008
Springer
15 years 2 months ago
2008
Springer
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....
132
Voted
GRAPHICSINTERFACE
2003
15 years 1 months ago
2003
We present a novel algorithm for simultaneous visual hull reconstruction and rendering by exploiting off-theshelf graphics hardware. The reconstruction is accomplished by projecti...
111
Voted
FPGA
2012
ACM
13 years 8 months ago
2012
ACM
Memory bandwidth is critical to achieving high performance in many FPGA applications. The bandwidth of SDRAM memories is, however, highly dependent upon the order in which address...