2 search results - page 1 / 1 » Acceleration of SAT-Based Iterative Property Checking |
84
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CHARME
2005
Springer
15 years 5 months ago
2005
Springer
Today, verification is becoming the dominating factor for successful circuit designs. In this context formal verification techniques allow to prove the correctness of a circuit ...
139
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VLSID
2010
IEEE
14 years 10 months ago
2010
IEEE
Directed test generation is important for the functional verification of complex system-on-chip designs. SAT based bounded model checking is promising for counterexample generatio...