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DFT
2007
IEEE
104views VLSI» more  DFT 2007»
15 years 6 months ago
Reduction of Fault Latency in Sequential Circuits by using Decomposition
The paper discusses a novel approach for reduction of fault detection latency in a selfchecking sequential circuit. The Authors propose decomposing the finite state machine (FSM) ...
Ilya Levin, Benjamin Abramov, Vladimir Ostrovsky
ICMCS
1996
IEEE
104views Multimedia» more  ICMCS 1996»
15 years 4 months ago
Design and Performance Tradeoffs in Clustered Video Servers
In this paper, we investigate the suitability of clustered architectures for designing scalable multimedia servers. Specifically, we evaluate the effects of: (i) architectural des...
Renu Tewari, Rajat Mukherjee, Daniel M. Dias, Harr...
EUROGP
2000
Springer
177views Optimization» more  EUROGP 2000»
15 years 3 months ago
Register Based Genetic Programming on FPGA Computing Platforms
The use of FPGA based custom computing platforms is proposed for implementing linearly structured Genetic Programs. Such a context enables consideration of micro architectural and ...
Malcolm I. Heywood, A. Nur Zincir-Heywood
ISPASS
2006
IEEE
15 years 5 months ago
Comparing multinomial and k-means clustering for SimPoint
SimPoint is a technique used to pick what parts of the program’s execution to simulate in order to have a complete picture of execution. SimPoint uses data clustering algorithms...
Greg Hamerly, Erez Perelman, Brad Calder
SPIN
2004
Springer
15 years 5 months ago
Validation of UML Models via a Mapping to Communicating Extended Timed Automata
Abstract. We present a technique and a tool for model-checking operational UML models based on a mapping of object oriented UML models into a framework of communicating extended ti...
Iulian Ober, Susanne Graf, Ileana Ober