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FCCM
2007
IEEE
117views VLSI» more  FCCM 2007»
15 years 8 months ago
FPGA Acceleration of Gene Rearrangement Analysis
In this paper we present our work toward FPGA acceleration of phylogenetic reconstruction, a type of analysis that is commonly performed in the fields of systematic biology and co...
Jason D. Bakos
CODES
2005
IEEE
15 years 7 months ago
Novel architecture for loop acceleration: a case study
In this paper, we show a novel approach to accelerate loops by tightly coupling a coprocessor to an ASIP. Latency hiding is used to exploit the parallelism available in this archi...
Seng Lin Shee, Sri Parameswaran, Newton Cheung
SASP
2009
IEEE
238views Hardware» more  SASP 2009»
15 years 8 months ago
Hardware acceleration of multi-view face detection
—This paper presents a parallelized architecture for hardware acceleration of multi-view face detection. In our architecture, the multi-view face detection system generates rotat...
Junguk Cho, Bridget Benson, Ryan Kastner
CIBCB
2007
IEEE
15 years 5 months ago
Hybrid Architecture for Accelerating DNA Codeword Library Searching
-- A large and reliable DNA codeword library is the key to the success of DNA based computing. Searching for the set of reliable DNA codewords is an NP-hard problem, which can take...
Qinru Qiu, Daniel J. Burns, Qing Wu, Prakash Mukre
126
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ERSA
2009
131views Hardware» more  ERSA 2009»
14 years 11 months ago
Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays
An effective way to implement image processing applications is to use embedded processors with dynamically reconfigurable accelerator cores. The processing speed of these processor...
Hasitha Muthumala Waidyasooriya, Masanori Hariyama...