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ARC
2008
Springer
104views Hardware» more  ARC 2008»
15 years 3 months ago
PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....
Frank Hannig, Holger Ruckdeschel, Hritam Dutta, J&...
GRAPHICSINTERFACE
2003
15 years 2 months ago
Hardware-Accelerated Visual Hull Reconstruction and Rendering
We present a novel algorithm for simultaneous visual hull reconstruction and rendering by exploiting off-theshelf graphics hardware. The reconstruction is accomplished by projecti...
Ming Li, Marcus A. Magnor, Hans-Peter Seidel
ICASSP
2011
IEEE
14 years 5 months ago
Real-time DVB-S2 LDPC decoding on many-core GPU accelerators
It is well known that LDPC decoding is computationally demanding and one of the hardest signal operations to parallelize. Beyond data dependencies that restrict the decoding of a ...
Gabriel Falcão Paiva Fernandes, Joao Andrad...
FPGA
2012
ACM
285views FPGA» more  FPGA 2012»
13 years 9 months ago
Optimizing SDRAM bandwidth for custom FPGA loop accelerators
Memory bandwidth is critical to achieving high performance in many FPGA applications. The bandwidth of SDRAM memories is, however, highly dependent upon the order in which address...
Samuel Bayliss, George A. Constantinides
PKDD
2004
Springer
90views Data Mining» more  PKDD 2004»
15 years 7 months ago
Shape and Size Regularization in Expectation Maximization and Fuzzy Clustering
The more sophisticated fuzzy clustering algorithms, like the Gustafson–Kessel algorithm [11] and the fuzzy maximum likelihood estimation (FMLE) algorithm [10] offer the possibil...
Christian Borgelt, Rudolf Kruse