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PROMISE
2010
13 years 1 months ago
Defect cost flow model: a Bayesian network for predicting defect correction effort
Background. Software defect prediction has been one of the central topics of software engineering. Predicted defect counts have been used mainly to assess software quality and est...
Thomas Schulz, Lukasz Radlinski, Thomas Gorges, Wo...
JNCA
2008
95views more  JNCA 2008»
13 years 6 months ago
Techniques to support Web Service selection and consumption with QoS characteristics
This work proposes a Web Service (WS) discovery model in which the functional and nonfunctional requirements are taken into account during service discovery. The proposed infrastr...
Vassiliki Diamadopoulou, Christos Makris, Yannis P...
VTS
1998
IEEE
98views Hardware» more  VTS 1998»
13 years 10 months ago
Experimental Results for IDDQ and VLV Testing
An experimental test chip was designed and manufactured to evaluate different test techniques. Based on the results presented in the wafer probe, 309 out of 5491 dies that passed ...
Jonathan T.-Y. Chang, Chao-Wen Tseng, Yi-Chin Chu,...
ITC
1996
IEEE
96views Hardware» more  ITC 1996»
13 years 10 months ago
Analysis and Detection of Timing Failures in an Experimental Test Chip
A 25k gate Test Chip was designed and manufactured to evaluate different test methods for scan-designed circuits. The design of the chip, the experiment, and preliminary experimen...
Piero Franco, Siyad C. Ma, Jonathan Chang, Yi-Chin...
DFT
1998
IEEE
88views VLSI» more  DFT 1998»
13 years 10 months ago
Characterization of CMOS Defects using Transient Signal Analysis
We present the results of hardware experiments designed to determine the relative contribution of CMOS coupling mechanisms to off-path signal variations caused by common types of ...
James F. Plusquellic, Donald M. Chiarulli, Steven ...