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» Accuracy-Adaptive Simulation of Transaction Level Models
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DATE
2003
IEEE
117views Hardware» more  DATE 2003»
15 years 2 months ago
Exploring SW Performance Using SoC Transaction-Level Modeling
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
Imed Moussa, Thierry Grellier, Giang Nguyen
ISQED
2006
IEEE
90views Hardware» more  ISQED 2006»
15 years 3 months ago
Transaction Level Error Susceptibility Model for Bus Based SoC Architectures
System on Chip architectures have traditionally relied upon bus based interconnect for their communication needs. However, increasing bus frequencies and the load on the bus calls...
Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykr...
81
Voted
CODES
2006
IEEE
15 years 3 months ago
Automatic generation of transaction level models for rapid design space exploration
Transaction-level modeling has been touted to improve simulation performance and modeling efficiency for early design space exploration. But no tools are available to generate suc...
Dongwan Shin, Andreas Gerstlauer, Junyu Peng, Rain...
DATE
2009
IEEE
126views Hardware» more  DATE 2009»
15 years 4 months ago
Fast and accurate protocol specific bus modeling using TLM 2.0
—The need to have Transaction Level models early in the design cycle is becoming more and more important to shorten the development times of complex Systems-on-Chip (SoC). These ...
H. W. M. van Moll, Henk Corporaal, Víctor R...
FDL
2006
IEEE
15 years 3 months ago
Formalizing TLM with Communicating State Machines
Transaction Level Models are widely being used as high-level reference models during embedded systems development. High simulation speed and great modeling flexibility are the ma...
Bernhard Niemann, Christian Haubelt