380 search results - page 14 / 76 » Accurate Predictive Interconnect Modeling for System-Level D... |
DATE
2009
IEEE
15 years 6 months ago
2009
IEEE
— As clock frequencies exceed giga-Hertz, the extra power loss due to conductor surface roughness in interconnects and packagings is more evident and thus demands a proper accou...
106
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DAC
2008
ACM
16 years 20 days ago
2008
ACM
Current source based cell models are becoming a necessity for accurate timing and noise analysis at 65nm and below. Voltage waveform shapes are increasingly more difficult to repr...
DAC
2002
ACM
16 years 19 days ago
2002
ACM
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
ICCAD
2004
IEEE
15 years 8 months ago
2004
IEEE
9, IO]. However, unlike the case with static timing, it is not so easy We show how recent advances in the handling of correlated interval representations of range uncertainty can b...
104
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MEMOCODE
2003
IEEE
15 years 5 months ago
2003
IEEE
In the design process of SoC (System on Chip), validation is one of the most critical and costly activity. The main problem for industrial companies like STMicroelectronics, stand...