380 search results - page 15 / 76 » Accurate Predictive Interconnect Modeling for System-Level D... |
192
Voted
ISQED
2011
IEEE
14 years 3 months ago
2011
IEEE
As process technology continues to shrink, interconnect current densities continue to increase, making it ever more difficult to meet chip reliability targets. For microprocessors...
101
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EURODAC
1994
IEEE
15 years 3 months ago
1994
IEEE
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...
99
Voted
ASPDAC
2010
ACM
14 years 9 months ago
2010
ACM
In this paper, we propose a new wideband model order reduction method for interconnect circuits by using a novel adaptive sampling and error estimation scheme. We try to address t...
94
Voted
ISPD
2007
ACM
15 years 1 months ago
2007
ACM
In this paper, we propose fast and efficient techniques to analyze the power grid with accurate modeling of the transistor network. The solution techniques currently available for...
DAC
1999
ACM
16 years 19 days ago
1999
ACM
In this paper we present a new algorithm for computing reduced-order models of interconnect which utilizes the dominant controllable subspace of the system. The dominant controlla...