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GLVLSI
2003
IEEE
134views VLSI» more  GLVLSI 2003»
15 years 5 months ago
Modeling QCA for area minimization in logic synthesis
Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device impro...
Nadine Gergel, Shana Craft, John Lach
ICCAD
2002
IEEE
106views Hardware» more  ICCAD 2002»
15 years 8 months ago
Throughput-driven IC communication fabric synthesis
As the scale of system integration continues to grow, the on-chip communication becomes the ultimate bottleneck of system performance and the primary determinant of system archite...
Tao Lin, Lawrence T. Pileggi
CSE
2009
IEEE
15 years 6 months ago
On the Design of a Suitable Hardware Platform for Protocol Stack Processing in LTE Terminals
—In this paper we present a design methodology for the identification and development of a suitable hardware platform (including dedicated hardware accelerators) for the data pl...
Sebastian Hessel, David Szczesny, Shadi Traboulsi,...
EUROPAR
2009
Springer
15 years 6 months ago
PSINS: An Open Source Event Tracer and Execution Simulator for MPI Applications
The size of supercomputers in numbers of processors is growing exponentially. Today’s largest supercomputers have upwards of a hundred thousand processors and tomorrow’s may ha...
Mustafa M. Tikir, Michael Laurenzano, Laura Carrin...
DSD
2009
IEEE
152views Hardware» more  DSD 2009»
15 years 3 months ago
ARROW - A Generic Hardware Fault Injection Tool for NoCs
Todays NoCs are reaching a level where it is getting very hard to ensure 100% of functionality. Consequently, fault tolerance has become an important aspect in todays design techn...
Michael Birner, Thomas Handl