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DATE
2005
IEEE
154views Hardware» more  DATE 2005»
15 years 3 months ago
A Time Slice Based Scheduler Model for System Level Design
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
Luciano Lavagno, Claudio Passerone, Vishal Shah, Y...
CODES
2006
IEEE
15 years 3 months ago
Accurate yet fast modeling of real-time communication
Accurate modeling of communication is a necessary part of system level design for real-time safety-critical applications. For efficient prediction of a system’s performance, Tra...
Gunar Schirner, Rainer Dömer
ICCD
2007
IEEE
133views Hardware» more  ICCD 2007»
15 years 6 months ago
System level power estimation methodology with H.264 decoder prediction IP case study
This paper presents a methodology to generate a hierarchy of power models for power estimation of custom hardware IP blocks, enabling a trade-off between power estimation accuracy...
Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi,...
DATE
2003
IEEE
123views Hardware» more  DATE 2003»
15 years 2 months ago
RTOS Modeling for System Level Design
System level synthesis is widely seen as the solution for closing the productivity gap in system design. High level system models are used in system level design for early design ...
Andreas Gerstlauer, Haobo Yu, Daniel Gajski
CODES
2006
IEEE
15 years 3 months ago
Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations
Process variability has a detrimental impact on the performance of memories and other system components, which can lead to parametric yield loss at the system level due to timing ...
Antonis Papanikolaou, T. Grabner, Miguel Miranda, ...