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ICCAD
2001
IEEE
111views Hardware» more  ICCAD 2001»
15 years 10 months ago
Congestion Aware Layout Driven Logic Synthesis
In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitionin...
Thomas Kutzschebauch, Leon Stok
PEPM
2009
ACM
15 years 10 months ago
Program analysis for bug detection using parfait: invited talk
The goal of the Parfait project is to find bugs in C source code in a scalable and precise way. To this end, Parfait was designed as a framework with layers of sound program anal...
Cristina Cifuentes, Nathan Keynes, Lian Li, Bernha...
DAC
2009
ACM
15 years 8 months ago
On-line thermal aware dynamic voltage scaling for energy optimization with frequency/temperature dependency consideration
With new technologies, temperature has become a major issue to be considered at system level design. Without taking temperature aspects into consideration, no approach to energy o...
Min Bao, Alexandru Andrei, Petru Eles, Zebo Peng
DATE
2009
IEEE
118views Hardware» more  DATE 2009»
15 years 8 months ago
Gate sizing for large cell-based designs
—Today, many chips are designed with predefined discrete cell libraries. In this paper we present a new fast gate sizing algorithm that works natively with discrete cell choices...
Stephan Held
ICC
2009
IEEE
121views Communications» more  ICC 2009»
15 years 8 months ago
Idle Channel Time Estimation in Multi-Hop Wireless Networks
—This paper presents a theoretical estimation for idle channel time in a multi-hop environment. Idle channel time is the time proportion of a node during which the channel state ...
Simon Odou, Steven Martin, Khaldoun Al Agha