Sciweavers

276 search results - page 17 / 56
» Accurate and Efficient Static Timing Analysis with Crosstalk
Sort
View
DATE
2002
IEEE
102views Hardware» more  DATE 2002»
15 years 4 months ago
Library Compatible Ceff for Gate-Level Timing
Accurate gate-level static timing analysis in the presence of RC loads has become an important problem for modern deep-submicron designs. Non-capacitive loads are usually analyzed...
Bernard N. Sheehan
ICCAD
1999
IEEE
115views Hardware» more  ICCAD 1999»
15 years 3 months ago
Fast performance analysis of bus-based system-on-chip communication architectures
This paper addresses the problem of efficient and accurate performance analysis to drive the exploration and design of bus-based System-on-Chip (SOC) communication architectures. ...
Kanishka Lahiri, Anand Raghunathan, Sujit Dey
RTAS
1996
IEEE
15 years 3 months ago
Efficient worst case timing analysis of data caching
Recent progress in worst case timing analysis of programs has made it possible to perform accurate timing analysis of pipelined execution and instruction caching, which is necessa...
Sung-Kwan Kim, Sang Lyul Min, Rhan Ha
ASPDAC
2008
ACM
200views Hardware» more  ASPDAC 2008»
15 years 1 months ago
Non-Gaussian statistical timing analysis using second-order polynomial fitting
In the nanometer manufacturing region, process variation causes significant uncertainty for circuit performance verification. Statistical static timing analysis (SSTA) is thus dev...
Lerong Cheng, Jinjun Xiong, Lei He
CODES
2009
IEEE
15 years 3 months ago
Cycle count accurate memory modeling in system level design
In this paper, we propose an effective automatic generation approach for a Cycle-Count Accurate Memory Model (CCAMM) from the Clocked Finite State Machine (CFSM) of the Cycle Accu...
Yi-Len Lo, Mao Lin Li, Ren-Song Tsay