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» Accurate and scalable reliability analysis of logic circuits
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107
Voted
DSD
2007
IEEE
105views Hardware» more  DSD 2007»
15 years 6 months ago
Scaling Analytical Models for Soft Error Rate Estimation Under a Multiple-Fault Environment
With continuing increase in soft error rates, its foreseeable that multiple faults will eventually need to be considered when modeling circuit sensitivity and evaluating faulttole...
Christian J. Hescott, Drew C. Ness, David J. Lilja
DAC
2012
ACM
13 years 2 months ago
Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs
In this work, we propose a fast and accurate chip/package thermomechanical stress and reliability co-analysis tool for TSV-based 3D ICs. We also present a design optimization meth...
Moongon Jung, David Z. Pan, Sung Kyu Lim
89
Voted
ISQED
2010
IEEE
128views Hardware» more  ISQED 2010»
15 years 4 months ago
Soft error rate determination for nanoscale sequential logic
We analyze the neutron induced soft error rate (SER) by modeling induced error pulse using two parameters, occurrence frequency and probability density function for the pulse widt...
Fan Wang, Vishwani D. Agrawal
ISQED
2006
IEEE
136views Hardware» more  ISQED 2006»
15 years 5 months ago
An Improved AMG-based Method for Fast Power Grid Analysis
The continuing VLSI technology scaling leads to increasingly significant power supply fluctuations, which need to be modeled accurately in circuit design and verification. Meanwhi...
Cheng Zhuo, Jiang Hu, Kangsheng Chen
DAC
2007
ACM
16 years 20 days ago
Statistical Analysis of Full-Chip Leakage Power Considering Junction Tunneling Leakage
In this paper we address the the growing issue of junction tunneling leakage (Ijunc) at the circuit level. Specifically, we develop a fast approach to analyze the state-dependent ...
Tao Li, Zhiping Yu