130 search results - page 12 / 26 » Accurate and scalable reliability analysis of logic circuits |
DAC
2006
ACM
16 years 19 days ago
2006
ACM
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...
140
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DAC
2006
ACM
16 years 19 days ago
2006
ACM
- Classical two-variable symmetries play an important role in many EDA applications, ranging from logic synthesis to formal verification. This paper proposes a complete circuit-bas...
DATE
2010
IEEE
15 years 4 months ago
2010
IEEE
With aggressive gate oxide scaling, latent defects in the gate oxide manifest as traps that, in time, lead to gate oxide breakdown. Progressive gate oxide breakdown, also referred...
CEC
2008
IEEE
15 years 6 months ago
2008
IEEE
— This work is part of a project that aims to develop and operate integrated evolvable hardware systems using unconstrained evolution. Experiments are carried out on an evolvable...
113
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DAC
2006
ACM
15 years 5 months ago
2006
ACM
Negative bias temperature instability (NBTI) has become the dominant reliability concern for nanoscale PMOS transistors. In this paper, a predictive model is developed for the deg...