130 search results - page 15 / 26 » Accurate and scalable reliability analysis of logic circuits |
ISQED
2005
IEEE
15 years 5 months ago
2005
IEEE
This paper presents a methodology for accurate propagation of delay information through a gate for the purpose of static timing analysis (STA) in the presence of noise. Convention...
ICCAD
2007
IEEE
15 years 8 months ago
2007
IEEE
While the increasing need for addressing process variability in sub-90nm VLSI technologies has sparkled a large body of statistical timing and optimization research, the realizati...
117
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VTS
2005
IEEE
15 years 5 months ago
2005
IEEE
— A closed-form model for simulation and analysis of voltage transients caused by single-event upsets (SEUs) in logic circuits is described. A linear RC model, derived using a SP...
VTS
2007
IEEE
15 years 6 months ago
2007
IEEE
Soft errors due to cosmic particles are a growing reliability threat for VLSI systems. In this paper we analyze the soft error vulnerability of FPGAs used in storage systems. Sinc...
106
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GLVLSI
2007
IEEE
14 years 12 months ago
2007
IEEE
This paper reviews the modeling of subthreshold leakage current and proposes an improved model for general series-parallel CMOS networks. The presence of on-switches in off-networ...