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» Accurate and scalable reliability analysis of logic circuits
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CAV
2000
Springer
197views Hardware» more  CAV 2000»
15 years 4 months ago
Bounded Model Construction for Monadic Second-Order Logics
Address: Abstraction, Composition, Symmetry, and a Little Deduction: The Remedies to State Explosion . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A. Pnueli Invited Address...
Abdelwaheb Ayari, David A. Basin
ASYNC
2000
IEEE
122views Hardware» more  ASYNC 2000»
15 years 4 months ago
DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits
Fault Abstraction and Collapsing Framework for Asynchronous Circuits Philip P. Shirvani, Subhasish Mitra Center for Reliable Computing Stanford University Stanford, CA Jo C. Eberge...
Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen...
DAC
2001
ACM
16 years 21 days ago
Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
Kaustav Banerjee, Amit Mehrotra
ICCD
2004
IEEE
138views Hardware» more  ICCD 2004»
15 years 8 months ago
Design and Implementation of Scalable Low-Power Montgomery Multiplier
In this paper, an efficient Montgomery multiplier is introduced for the modular exponentiation operation, which is fundamental to numerous public-key cryptosystems. Four aspects a...
Hee-Kwan Son, Sang-Geun Oh
DFT
2007
IEEE
105views VLSI» more  DFT 2007»
15 years 6 months ago
A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction
Decreasing feature sizes have led to an increased vulnerability of random logic to soft errors. A particle strike may cause a glitch or single event transient (SET) at the output ...
Sybille Hellebrand, Christian G. Zoellin, Hans-Joa...