81 search results - page 4 / 17 » Accurate microarchitecture-level fault modeling for studying... |
DAC
2011
ACM
12 years 6 months ago
2011
ACM
Process Variation (PV) is increasingly threatening the reliability of Networks-on-Chips. Thus, various resilient router designs have been recently proposed and evaluated. However,...
DSD
2007
IEEE
14 years 17 days ago
2007
IEEE
With continuing increase in soft error rates, its foreseeable that multiple faults will eventually need to be considered when modeling circuit sensitivity and evaluating faulttole...
DFT
2000
IEEE
13 years 10 months ago
2000
IEEE
Many fault-tolerant architectures are based on the single-fault assumption, hence accumulation of dormant faults represents a potential reliability hazard. Based on the example of...
ICCD
1997
IEEE
13 years 10 months ago
1997
IEEE
: This paper studies pseudo-random pattern testing of bridging faults. Although bridging faults are generally more random pattern testable than stuck-at faults, examples are shown ...
DATE
2000
IEEE
13 years 10 months ago
2000
IEEE
We study the effectiveness of functional tests for full scan circuits. Functional tests are important for design validation, and they potentially have a high defect coverage indep...