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DATE
2004
IEEE
142views Hardware» more  DATE 2004»
15 years 1 months ago
Eliminating False Positives in Crosstalk Noise Analysis
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. Noise analysis techniques can detect some of such noise faults, but accu...
Yajun Ran, Alex Kondratyev, Yosinori Watanabe, Mal...
TVLSI
2008
139views more  TVLSI 2008»
14 years 9 months ago
Ternary CAM Power and Delay Model: Extensions and Uses
Applications in computer networks often require high throughput access to large data structures for lookup and classification. While advanced algorithms exist to speed these search...
Banit Agrawal, Timothy Sherwood
HPCA
2009
IEEE
15 years 10 months ago
Accurate microarchitecture-level fault modeling for studying hardware faults
Decreasing hardware reliability is expected to impede the exploitation of increasing integration projected by Moore's Law. There is much ongoing research on efficient fault t...
Man-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu...
DATE
2006
IEEE
158views Hardware» more  DATE 2006»
15 years 3 months ago
Modeling multiple input switching of CMOS gates in DSM technology using HDMR
Abstract— Continuing scaling of CMOS technology has allowed aggressive pursuant of increased clock rate in DSM chips. The ever shorter clock period has made switching times of di...
Jayashree Sridharan, Tom Chen
BMCBI
2010
110views more  BMCBI 2010»
14 years 9 months ago
TimeDelay-ARACNE: Reverse engineering of gene networks from time-course data by an information theoretic approach
Background: One of main aims of Molecular Biology is the gain of knowledge about how molecular components interact each other and to understand gene function regulations. Using mi...
Pietro Zoppoli, Sandro Morganella, Michele Ceccare...