48 search results - page 7 / 10 » Accurate timing analysis using SAT and pattern-dependent del... |
100
click to vote
INFOCOM
2010
IEEE
14 years 7 months ago
2010
IEEE
We investigate the fundamental capacity limits of space-time journeys of information in mobile and Delay Tolerant Networks (DTNs), where information is either transmitted or carrie...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper focuses on statistical interconnect timing analysis in a parameterized block-based statistical static timing analysis tool. In particular, a new framework for performin...
DATE
2010
IEEE
15 years 2 months ago
2010
IEEE
—Variations of process parameters have an important impact on reliability and yield in deep sub micron IC technologies. One methodology to estimate the influence of these effects...
ICCAD
2003
IEEE
15 years 2 months ago
2003
IEEE
The impact of power supply integrity on a design has become a critical issue, not only for functional verification, but also for performance verification. Traditional analysis has...
ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
Static timing analysis is a critical step in design of any digital integrated circuit. Technology and design trends have led to significant increase in environmental and process v...