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ISCA
2003
IEEE
96views Hardware» more  ISCA 2003»
15 years 4 months ago
Parallelism in the Front-End
As processor back-ends get more aggressive, front-ends will have to scale as well. Although the back-ends of superscalar processors have continued to become more parallel, the fro...
Paramjit S. Oberoi, Gurindar S. Sohi
MICRO
2008
IEEE
138views Hardware» more  MICRO 2008»
15 years 6 months ago
Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs
As the number of transistors integrated on a chip continues to increase, a growing challenge is accurately modeling performance in the early stages of processor design. Analytical...
Xi E. Chen, Tor M. Aamodt
ISCA
2002
IEEE
127views Hardware» more  ISCA 2002»
15 years 4 months ago
The Optimum Pipeline Depth for a Microprocessor
The impact of pipeline length on the performance of a microprocessor is explored both theoretically and by simulation. An analytical theory is presented that shows two opposing ar...
Allan Hartstein, Thomas R. Puzak
89
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LCPC
2004
Springer
15 years 5 months ago
Branch Strategies to Optimize Decision Trees for Wide-Issue Architectures
Abstract. Branch predictors are associated with critical design issues for nowadays instruction greedy processors. We study two important domains where the optimization of decision...
Patrick Carribault, Christophe Lemuet, Jean-Thomas...
EUROSYS
2008
ACM
15 years 8 months ago
BorderPatrol: isolating events for black-box tracing
Causal request traces are valuable to developers of large concurrent and distributed applications, yet difficult to obtain. Traces show how a request is processed, and can be anal...
Eric Koskinen, John Jannotti