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ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
15 years 5 months ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
IPSN
2007
Springer
15 years 5 months ago
FlashDB: dynamic self-tuning database for NAND flash
FlashDB is a self-tuning database optimized for sensor networks using NAND flash storage. In practical systems flash is used in different packages such as on-board flash chips,...
Suman Nath, Aman Kansal
SENSYS
2006
ACM
15 years 5 months ago
Virtual high-resolution for sensor networks
The resolution at which a sensor network collects data is a crucial parameter of performance since it governs the range of applications that are feasible to be developed using tha...
Aman Kansal, William J. Kaiser, Gregory J. Pottie,...
ASPLOS
2000
ACM
15 years 3 months ago
Symbiotic Jobscheduling for a Simultaneous Multithreading Processor
Simultaneous Multithreading machines fetch and execute instructions from multiple instruction streams to increase system utilization and speedup the execution of jobs. When there ...
Allan Snavely, Dean M. Tullsen
CF
2007
ACM
15 years 3 months ago
Accelerating memory decryption and authentication with frequent value prediction
This paper presents a novel architectural technique to hide fetch latency overhead of hardware encrypted and authenticated memory. A number of recent secure processor designs have...
Weidong Shi, Hsien-Hsin S. Lee