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IEEEPACT
2006
IEEE
15 years 5 months ago
Overlapping dependent loads with addressless preload
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
Zhen Yang, Xudong Shi, Feiqi Su, Jih-Kwon Peir
IJCNN
2006
IEEE
15 years 5 months ago
Design of Optimal PI Controllers for Doubly Fed Induction Generators Driven by Wind Turbines Using Particle Swarm Optimization
– When subjected to transient disturbances in the power grid, the variable frequency converter (VFC) is the most sensitive part in the variable-speed wind turbine generator syste...
Wei Qiao, Ganesh K. Venayagamoorthy, Ronald G. Har...
INFOCOM
2006
IEEE
15 years 5 months ago
Bandwidth Sharing with Primary Paths for Protection Routing in an MPLS Network
Abstract— In label-switched networks such as MPLS, protection routing involves computing and setting up the backup paths at the same time when the primary paths are routed. It ha...
Faisal Aslam, Saqib Raza, Zartash Afzal Uzmi, Youn...
IPPS
2006
IEEE
15 years 5 months ago
Composite Abortable Locks
The need to allow threads to abort an attempt to acquire a lock (sometimes called a timeout) is an interesting new requirement driven by state-of-the-art database applications wit...
Virendra J. Marathe, Mark Moir, Nir Shavit
ISPD
2006
ACM
90views Hardware» more  ISPD 2006»
15 years 5 months ago
Fast buffer insertion considering process variations
Advanced process technologies call for a proactive consideration of process variations in design to ensure high parametric timing yield. Despite of its popular use in almost any h...
Jinjun Xiong, Lei He